1. Field Of The Invention
The present invention relates to a serial-parallel converting circuit, and more specifically to a serial-parallel converting circuit suitable for use in CMOS (complementary motel oxide semiconductor field effect transistor) LSI (large scaled integrated circuit).
2. Description of Related Art
A conventional serial-parallel converting circuit basically comprises a shift register circuit receiving a serial data and a clock signal so as to shift the received serial data through the shift register in response to each clock signal, and an output register circuit coupled in parallel to respective stages of the shift register circuit so as to fetch the content of the shift register circuit in response to a frequency-divided clock supplied from a frequency dividing circuit. Ordinary, the frequency dividing circuit receives the clock signal, and supplies the frequency-divided clock through a buffer to the output register circuit.
In the above mentioned serial-parallel converting circuit, the operation speed is limited by a maximum operation speed of the frequency dividing circuit. In this connection, the buffer supplying the frequency-divided clock to the output register circuit gives some delay. However, this delay can be made ignorable, by making a transfer delay from the shift register circuit to the output register circuit, consistent with the delay of the buffer. However, since the frequency dividing circuit is a counter constituted of a sequential circuit having a feedback loop, the operation speed cannot be equivalently increased by a method similar to the above mentioned matching of the delay time.
In addition, the feedback loop of the frequency dividing circuit includes therein a multi-input logic gate such as an exclusive-NOR gate. In the case that the serial-parallel converting circuit is formed in accordance with a CMOS LSI technology, the delay time of the exclusive-NOR gate substantially determines or dominates the delay time of the frequency dividing circuit.
Furthermore, if a parallel development number, namely, the number of parallel outputs is increased, the frequency dividing circuit becomes complicated in construction, and the maximum operation speed of the frequency dividing circuit is lowered.